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Documentation for Tape-out
1.2 TSMC N12 Implementation
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Documentation for Tape-out
GitHub Repo
Welcome to Tape-out Docs!
I. EDA Tools & Environment
II. Frontend
II. Frontend
1. RTL Design
1. RTL Design
1.1 SRAM IP Specification
1.2 FPU IP Specification
1.3 System Integration
2. Submodule Synthesis
2. Submodule Synthesis
2.1 TSMC N22 Synthesis
2.2 TSMC N12 Synthesis
III. Backend
III. Backend
1. Submodule Physical Implementation
1. Submodule Physical Implementation
1.1 TSMC N22 Implementation
1.2 TSMC N12 Implementation
1.2 TSMC N12 Implementation
目录
1. 说明
2. TOP IO Implementation
2. TOP IO Implementation
2.1 TSMC N22 Implementation
2.2 TSMC N12 Implementation
3. Physical Verification
3. Physical Verification
3.1 Block-Level Verification
3.2 Top-Level Verification
4. Tape-out
IV. Verification
IV. Verification
1. Subsystem Simulation
2. FPGA Verification
3. STA & Power
V. Post-tapeout
V. Post-tapeout
1. PCB
2. Packaging
3. Testing
3. Testing
3.1 Testing Equipment
3.2 RISC-V CPU Debugging
VI. Appendix
VI. Appendix
1. C Compiling
2. WSL
3. PDK Setup
4. Using DRAM on FPGA
5. Linux Environment & Common Tools
VII. Legacy
VII. Legacy
1. Behavioral Simulation (Deprecated)
2. Gate-Level Simulation (Deprecated)
3. Submodule Synthesis (Deprecated)
4. Submodule Synthesis (New)
5. Submodule Implementation (Deprecated)
6. Submodule Implementation (New)
7. Digital-CIM IP Specification (Deprecated)
VIII. Join Us! How to Contribute?
目录
1. 说明
数字子系统的物理设计（TSMC N12）
1. 说明
Under development!
Page Authors:
Bwoah-Kimi
(80.0%),
Siris-Li
(20.0%)
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