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Documentation for Tape-out

3. PDK Setup

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Documentation for Tape-out

Welcome to Tape-out Docs!
I. EDA Tools & Environment
II. Frontend
II. Frontend
- 1. RTL Design
  1. RTL Design
- 2. Submodule Synthesis
  2. Submodule Synthesis
  - 2.1 TSMC N22 Synthesis
  - 2.2 TSMC N12 Synthesis
III. Backend
III. Backend
- 1. Submodule Physical Implementation
  1. Submodule Physical Implementation
  - 1.1 TSMC N22 Implementation
  - 1.2 TSMC N12 Implementation
- 2. TOP IO Implementation
  2. TOP IO Implementation
  - 2.1 TSMC N22 Implementation
  - 2.2 TSMC N12 Implementation
- 3. Physical Verification
  3. Physical Verification
  - 3.1 Block-Level Verification
  - 3.2 Top-Level Verification
- 4. Tape-out
IV. Verification
IV. Verification
V. Post-tapeout
V. Post-tapeout
- 1. PCB
- 2. Packaging
- 3. Testing
  3. Testing
  - 3.1 Testing Equipment
  - 3.2 RISC-V CPU Debugging
VI. Appendix
VI. Appendix
VII. Legacy
VII. Legacy
VIII. Join Us! How to Contribute?

设置 PDK

Under development!

FIXME!!!

如何安装 PDK。

[./]

2026年3月3日 2024年10月10日

Hyouka0129, Bwoah-Kimi

GitHub

Page Authors: Hyouka0129 (85.71%), Bwoah-Kimi (14.29%)

4. Using DRAM on FPGA

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